U.S. Pat. No. 5,083,295 issued to Lammerts et al. (PHN 12,754) shows a circuit as specified in the preamble. The memory cells of a particular column in the known circuit are connected to a particular pair of bit lines. The bit lines are connected to the inputs of inverting logic gates that form a bistable element in the sense amplifier. Prior to accessing a particular cell of the column, the bit lines are precharged to a predetermined voltage level. When the specific cell is being read, it affects the voltages of the bit lines dependent on the cell's logic state. The sense amplifier then connects each respective one of the bit lines to a respective one of the power supply nodes under control of the resulting voltage difference in order to render the voltage difference more pronounced. Before a next sensing operation can be carried out, the bit lines have to be precharged again to the predetermined level.
Precharging for the full voltage swing is both time consuming and power consuming. Also, the known memory circuit needs static biasing of the bit lines and requires multiple control signals.